STABILIZATION OF Ni MONOSILICIDE THIN FILMS IN CMOS DEVICES USING IMPLANTATION OF IONS BEFORE SILICIDATION

ABSTRACT

A method for forming a stabilized metal silicide film, e.g., contact (source/drain or gate), that does not substantially agglomerate during subsequent thermal treatments, is provided. In the present invention, ions that are capable of attaching to defects within the Si-containing layer are implanted into the Si-containing layer prior to formation of metal silicide. The implanted ions stabilize the film, because the implants were found to substantially prevent agglomeration or at least delay agglomeration to much higher temperatures than in cases in which no implants were used.

RELATED APPLICATIONS

This application is a continuation of U.S. application Ser. No.11/551,647, filed Oct. 20, 2006, which is a divisional of U.S.application Ser. No. 10/838,377, filed May 4, 2004, now U.S. Pat. No.7,119,012, issued on Oct. 10, 2006.

FIELD OF THE INVENTION

The present invention relates to metal silicide films for complementarymetal oxide semiconductor (CMOS) devices, and more particularly to amethod of fabricating metal silicide films that exhibit little or noagglomeration during subsequent thermal processing.

BACKGROUND OF THE INVENTION

Current CMOS technology uses silicides as contacts to the source/drain(S/D) regions of the devices that are fabricated upon a Si-containingsubstrate. Examples of silicides with low resistivity and contactresistance that are currently being used as S/D contacts are the C54phase of TiSi₂, CoSi₂, and NiSi. All three of these silicides areintegrated using a self-aligned silicide process (i.e., a salicideprocess). This process consists of a blanket deposition of the metal(Ti, Co, or Ni) with a cap layer (such as TiN, Ti or W), annealing at afirst lower temperature to form a first silicide phase (i.e., the C49phase of TiSi, CoSi, or NiSi), selectively wet etching the cap layer andunreacted metal that is not in contact with silicon, and annealing at asecond higher temperature to form the low resistance metal silicidephase (the C54 phase of TiSi₂ or CoSi₂). For the low resistance NiSi,the second anneal is typically not needed.

The advantage of these particular silicides is that they all may beimplemented with the self-aligned process avoiding additionallithographic steps. One advantage of Ni silicides is that Nimonosilicide contacts are thinner than conventional Ti or Co silicidecontacts. A disadvantage of Ni silicide contacts is that the higherresistivity nickel disilicide phase is produced during high temperatureprocessing steps, rather than the preferred lower resistivity nickelmonosilicide, NiSi, phase. The formation of the nickel disilicide phaseis nucleation controlled. A disadvantage of forming nickel disilicidesis that it consumes twice the amount of Si than the preferred NiSiphase. Moreover, nickel disilicides produce a rougher silicide/Si waferinterface and also have a higher sheet resistivity than the preferredNiSi.

Another disadvantage of NiSi contacts is that they tend to agglomeratereadily at standard CMOS processing temperatures. The term “agglomerate”is used herein to denote that a very thin film of NiSi tends to gatherinto a mass or cluster at temperatures on the order of about 400° C. orhigher. The agglomeration problem is not limited to Ni silicides. Ittypically occurs for various thin films other than NiSi and is worst forlow melting point materials. Pt silicide is one example of anothersilicide that tends to agglomerate readily.

Preventing agglomeration is a key to getting the NiSi process to yieldadequately. Attempts have been made in the prior art to develop methodsfor preventing the agglomeration of NiSi. Most of these prior artapproaches use a binary or ternary Ni alloy. The alloy may be containedwithin the metal layer itself, or it can be formed atop the metal layersuch that during annealing diffusion and intermixing of alloy, metal andSi occurs. These alloys, however, require much addition work to definethe alloy concentrations and to develop adequate post silicide formationetches.

In addition to the use of Ni alloys, there have been some fairly recentpublications that have shown that BF₂ implants to form pFET regions canenhance NiSi formation compared with the nFET regions in which BF₂ wasnot implanted. See, for example, A. S. Wong, et al., Appl. Phys. Lett.81, 5138 (2002); S. K. Donthu, et al., Mater, Res. Soc. Symp. Proc. 716,465 (2002); and C. Lavoie, et al., Microelectronic Engineering 70 (2003)144-157. While these three publications show an improvement in the NiSiin BF₂ implanted regions they do not disclose the purposefulimplantation of F or other like ions into both n and p regions tostabilize NiSi formation and prevent agglomeration of NiSi. Implantationof BF₂ requires activation anneal for the B. Moreover, BF₂ implantationdoes not fix the agglomeration problem on nFETs.

In view of the above, there is a need for providing a new and improvedmethod to fabricate metal silicide films, e.g., NiSi films, that showlittle or no agglomeration upon further heat treatments.

SUMMARY OF THE INVENTION

The present invention provides a method for forming a stabilized metalsilicide film, e.g., contact (source/drain or gate), that does notsubstantially agglomerate during subsequent thermal treatments. In thepresent invention, ions are implanted into a Si-containing layer priorto formation of the metal silicide. The ions employed in the presentinvention are capable of attaching to defects within a Si-containinglayer thereby preventing the metal used in formation of the silicidefrom substantially diffusing into the Si-containing layer. In someembodiments, depending on the conditions of the implant, the ions canamorphize or partially amorphize a region in the Si-containing layer.Moreover, the ions employed in the present invention substantiallyprevent agglomeration, or at least delaying agglomeration to much highertemperatures than in cases in which no implants were used. Note that theions used to prevent agglomeration are implanted into the structurefollowing typical device ion implantation and activation annealing.Preventing agglomeration is key to getting the metal silicide process toyield adequately.

In broad terms, the present invention provides a method of forming astabilized metal silicide film, e.g., contact, which includes the stepsof implanting ions, after device ion implantation and activationannealing, that are capable of preventing agglomeration into a surfaceof a Si-containing layer; forming a metal layer atop the surface of theSi-containing layer containing the ions; and siliciding the metal layerand the Si-containing layer containing the ions to form a metal silicidefilm. In accordance with the present invention, the metal silicide filmformed by the aforementioned processing steps exhibits little or noagglomeration during subsequent thermal processing.

In some embodiments, a cap layer is formed atop the metal layer prior tosilicidation. The silicidation process step includes a first anneal,removal of the optional cap and unreacted metal layer and, if needed, asecond anneal. The second anneal is not typically needed for allsilicide formation, but can be used in instances in which a metal richphase is formed during the first anneal.

The method of the present invention described above can be used to formmetal silicide contacts of low resistivity atop source/drain diffusionregions and/or gate conductors of a CMOS device.

The implantation can occur during the implantation of the source/draindiffusion regions or in a separate step prior to metal deposition.

The method of the present invention provides a faster alternativesolution to the binary or ternary metal alloy approach of the prior artwithout the need to define alloy concentration or to develop new postsilicide formation etches.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a pictorial representation (through a cross sectional view) ofan initial structure that is employed in the present invention.

FIG. 2 is a pictorial representation (through a cross sectional view)illustrating the structure of FIG. 1 during implantation of ions.

FIG. 3 is a pictorial representation (through a cross sectional view)illustrating the structure of FIG. 2 after formation of a metal layerand an optional cap layer.

FIG. 4 is a pictorial representation (through a cross sectional view)illustrating the structure after annealing and removing of unreactedmetal.

FIGS. 5A-5B are plots showing the sheet resistance variation of NiSi ona blanket SOT layer using F⁺ implants. Specifically, FIG. 5A shows thesheet resistance data of NiSi on a blanket SOI layer using F⁺ implantsat 5 keV; FIG. 5B shows the sheet resistance data of NiSi on a blanketSOI layer using F⁺ implants at 5 keV plus annealing at 1000° C., 5seconds.

FIGS. 6A-6D are back-scattered SEMs of NiSi formed on a Si substrate.

DETAIL DESCRIPTION OF THE INVENTION

The present invention, which provides a method of forming a stabilizedmetal silicide film using implantation of ions after device ionimplantation and activation annealing, but before silicidation, will nowbe described in greater detail by referring to the drawings thataccompany the present application. The drawings, illustrate theformation of stabilized metal silicide contacts atop source/drainregions that are formed into a Si-containing substrate that has at leastone CMOS device located thereon. Although such an illustration is shown,the present invention can be used to form a metal silicide film on anyexposed Si-containing surface layer. The Si-containing surface layer maycomprise any Si-containing semiconductor material, or it may comprise apolysilicon layer or a SiGe layer that may be used as a gate electrodeof a CMOS device.

It should be noted that in the drawings that follow more than one CMOSdevice, i.e., transistor, can be formed atop the Si-containingsubstrate. Also, if the gate electrode is polysilicon or SiGe and thereis no hardmask located thereon, a metal silicide contact, in accordancewith the present invention, could be formed atop the gate electrode aswell.

FIG. 1 shows an initial structure 10 that can be employed in the presentinvention. Specifically, the initial structure 10 shown in FIG. 1comprises a Si-containing substrate (or layer) 12 having isolationregions 14 and source/drain diffusion regions 16 formed therein. Theinitial structure 10 of the present invention also includes a least onegate region 18 that includes a gate dielectric 20 and a gate conductor22, located on top of the Si-containing substrate 12. An optionalhardmask, not shown, can be located atop the gate conductor 22. In theembodiment shown, the gate region 18 also includes at least one spacer24 located on each sidewall thereof.

The Si-containing substrate (or layer) 12 of the initial structure 10shown in FIG. 1 comprises any silicon-containing semiconductor materialincluding, but not limited to: Si, SiGe, SiGeC, SiC, Si/SiGe, preformedsilicon-on-insulator (SOI) substrates, silicon germanium-on-insulatorand other like semiconductor materials. The Si-containing semiconductorsubstrate (or layer) 12 may be doped, undoped or contain doped andundoped regions therein.

The isolation regions 14 are typically formed first into theSi-containing substrate 12. The isolation regions 14 can be trenchisolation regions, as shown, or field oxide isolation regions. Thetrench isolation regions are formed utilizing a conventional trenchisolation process well known to those skilled in the art. For example,lithography, etching and filling of the trench with a trench dielectricmay be used in forming the trench isolation regions. Optionally, a linermay be formed in the trench prior to trench fill, a densification stepmay be performed after the trench fill and a planarization process mayfollow the trench fill as well. The field oxide regions may be formedutilizing a so-called local oxidation of silicon process.

After forming the isolation regions 14 within the Si-containingsubstrate 12, gate dielectric 20 is formed on the entire surface of theSi-containing substrate 12 including atop the isolation regions 14, ifit is a deposited dielectric. The gate dielectric 20 can be formed by athermal growing process such as, for example, oxidation, nitridation oroxynitridation. Alternatively, the gate dielectric 20 can be formed by adeposition process such as, for example, chemical vapor deposition(CVD), plasma-assisted CVD, atomic layer deposition (ALD), evaporation,reactive sputtering, chemical solution deposition and other likedeposition processes. The gate dielectric 20 may also be formedutilizing any combination of the above processes.

The gate dielectric 20 is comprised of an insulating material including,but not limited to: an oxide, nitride, oxynitride and/or silicate. Inone embodiment, it is preferred that the gate dielectric 20 is comprisedof an oxide such as, for example, SiO₂, HfO₂, ZrO₂, Al₂O₃ TiO₂, La₂O₃,SrTiO₃, LaAlO₃, and mixtures thereof including the addition of siliconand nitrogen.

The physical thickness of the gate dielectric 20 may vary, buttypically, the gate dielectric 20 has a thickness from about 0.5 toabout 10 nm, with a thickness from about 0.5 to about 3 nm being moretypical.

After forming the gate dielectric 20, a blanket layer of a gateelectrode material 22 is formed on the gate dielectric 20 utilizing aknown deposition process such as physical vapor deposition (PVD), CVD orevaporation. The gate electrode material 22 may comprise polysilicon,SiGe, a silicide or a metal. Preferably, the gate electrode 22 iscomprised of polySi. Examples of metals that can be used as the gateelectrode 22 include, but are not limited to: Al, W, Cu, Ti or otherlike conductive metals. The blanket layer of gate electrode material 22may be doped or undoped. If doped, an in-situ doping deposition processmay be employed. Alternatively, a doped gate electrode 22 can be formedby deposition, ion implantation and annealing.

The doping of the gate electrode 22 will shift the work function of thegate formed. Illustrative examples of doping ions include As, P, B, Sb,Bi, In, Al, Tl, Ga or mixtures thereof. The thickness, i.e., height, ofthe gate electrode material 22 deposited at this point of the presentinvention may vary depending on the deposition process employed.Typically, the gate electrode material 22 has a vertical thickness fromabout 20 to about 180 nm, with a thickness from about 40 to about 150 nmbeing more typical.

In some embodiments, an optional hardmask (not shown) may be formed atopthe gate electrode material 22 by utilizing a conventional depositionprocess. The optional hardmask can be comprised of a dielectric such asan oxide or nitride.

The blanket gate electrode material 22 (and optionally the gatedielectric 20) is typically, but not always, patterned by lithographyand etching so as to provide at least one gate region 18. Each gateregion 18 formed may have the same dimension, i.e., length, or they canhave variable dimensions to improve device performance. The lithographystep includes applying a photoresist to the upper surface of the blanketdeposited gate electrode material 22, exposing the photoresist to adesired pattern of radiation and developing the exposed photoresistutilizing a conventional resist developer. The pattern in thephotoresist is then transferred to the blanket layer of gate electrodematerial 22 utilizing a dry etching process. The patterned photoresistis removed after etching has been completed. In some embodiments, ahardmask may be formed prior to formation of the photoresist and used inpatterning the blanket layer of gate electrode material 22.

Suitable dry etching processes that can be used in the present inventionin forming the gate region 18 include, but are not limited to: reactiveion etching, ion beam etching, plasma etching or laser ablation. The dryetching process employed is typically selective to the underlying gatedielectric 20 therefore this etching step does not typically remove thegate dielectric 20. In some embodiments, this etching step may howeverbe used to remove portions of the gate dielectric 20 that are notprotected by the patterned gate region 18. The latter embodiment isdepicted in the drawings of the present application.

Next, at least one spacer 24 is formed on exposed sidewalls of each gateregion 18. The at least one spacer 24 is comprised of an insulator suchas an oxide, nitride, oxynitride and/or any combination thereof. The atleast one spacer 24 is formed by deposition and etching.

In addition to the one spacer 24, the present invention alsocontemplates a structure including multiple spacers. In particular, thepresent invention contemplates a structure including a first spacerhaving a first width and a second spacer having a second width whereinthe first width is narrower than the second width.

The width of the spacer must be sufficiently wide enough such that thesource/drain silicide contacts (to be subsequently formed) do notencroach underneath the edges of the gate electrode 22 into the channelregion of the transistor. Typically, the source/drain silicide contactsdo not encroach underneath the edges of the gate stack when the spacerhas a width, as measured at the bottom, from about 20 to about 80 mu.

After spacer formation, source/drain diffusion regions 16 are formedinto the substrate. Note that the source/drain diffusion regions 16include extension regions that are typically formed prior to spacerformation. The extensions are formed by ion implantation and annealing.The annealing step may be omitted and performed during activation, i.e.,annealing, of the source/drain diffusion regions 16. By combining bothactivations in a single anneal, the thermal budget of the overallprocess can be lowered. The source/drain diffusion regions 16 are formedutilizing ion implantation and an annealing step. The annealing stepserves to activate the dopants that were implanted by the previousimplant step(s). The conditions for the ion implantation and annealingare well known to those skilled in the art.

Next, and if not previously removed, the exposed portion of the gatedielectric 20 is removed utilizing a chemical etching process thatselectively removes the gate dielectric 20. This etching step stops onan upper surface of the Si-containing substrate 12 as well as an uppersurface of the isolation regions 14. Although any chemical etchant maybe used in removing the exposed portions of the gate dielectric 20, inone embodiment dilute hydrofluoric acid (DHF) is used.

The above processing steps describe one technique that can be employedin the present invention for forming gate region 18. Another techniquethat can be employed is a damascene process in which a dummy gate regionis first formed on the structure. After dummy gate formation, aplanarizing dielectric material such as, for example, an oxide, isdeposited and thereafter the structure is planarized to expose an uppersurface of the dummy gate region. The dummy gate region is thenselectively removed and gate region 18 is formed in the opening in whichthe dummy gate region was previously located. After formation of thegate region 18, the planarizing dielectric is etched back utilizing aconventional etching process.

Next, and as shown in FIG. 2, ions 25 are implanted into theSi-containing substrate 12. This ion implantation step may occur eitherduring the above mentioned implantation step (with the implantation ofsource/drain dopants), or it can be performed as a separate step priorto silicidation, as shown here. The ion implantation process may be ablanket ion implant, such as is shown in FIG. 2. Alternatively, aselective implantation process can be employed wherein a patterned mask,not shown, is used to implant the ions only into the source/drainregions 16. Alternatively, a mask can be used that allows for differentions and/or ion concentration to be implanted. The ions are implantedusing a conventional ion beam implanter that operates at standardconditions. When a blanket implantation is employed, ions 25 can also beimplanted into the gate electrode so as to alter the work functionthereof.

The ions are typically implanted at an energy from about 0.5 to about 5keV using an ion dose from about 5E13 to about 5E15 atoms/cm². Moretypically, the ions are implanted at an energy from about 1 to about 2keV using an ion dose from about 3E14 to about 3E15 atoms/cm². Theimplant is typically performed at a substrate temperature from aboutroom temperature to about 200° C., with a substrate temperature of aboutroom temperature being more typical. Note that the ion dose may varydepending on the specific ion being implanted.

The energy selected for the implantation of ions is such that most ofthe ion implants remains in the part of the Si-containing substrate 12that will be consumed during the silicidation process.

In some embodiments of the present invention, the implanted ions areannealed in an inert gas ambient such as He, Ar, N₂, Xe or mixturesthereof. This annealing is typically performed at a temperature fromabout 200° C. to about 1200° C. This annealing step is optional and doesnot need to be performed in all instances to obtain a stabilized metalsilicide that exhibits substantially no agglomeration. The annealing ofthe ions can be performed in some cases wherein the ions are implantedat a dose of about 1E15 atoms/cm² or greater.

The ions employed in the present invention are any ions that are capableof affecting the microstructure of the Si-containing layer by attachingto defects within a Si-containing layer thereby preventing the metalused in formation of the silicide from substantially diffusing into theSi-containing layer. In some embodiments depending on implantconditions, the implanted ions can form an amorphized or partiallyamorphized region in the Si-containing layer. Moreover, the ionsemployed in the present invention typically stabilize the metalsilicide, because they substantially prevent agglomeration, or at leastdelay agglomeration to much higher temperatures than in cases in whichno implants were used. Illustrative examples of ions that can beemployed in the present invention include, but are not limited to:halogens, including F, Br, and Cl, Si, H, Pt, Re, Rh, W, In and anycombination thereof. Of the various ions mentioned above, it is highlypreferred to use F ions.

The ions mentioned above are also capable of amorphizing or partiallyamorphizing the region implanted leading to both a modification in thediffusion properties and the perfect match of metal silicide with theSi-containing layer, thus preventing axiotaxy. A definition of axiotaxycan be found, for instance, in Nature, Vol. 426. p. 641 (2003).

After performing the above implantation of ions, a metal layer 26 and anoptional cap layer 28 can be formed providing the structure shown, forexample, in FIG. 3. As shown, the metal layer 26 is formed first andthen, if used, the optional cap layer 28 is formed. The metal layer 26is in contact with exposed portions of the Si-containing substrate 12,particularly, the metal layer 26 is contact with the exposedSi-containing substrate 12 at the source/drain diffusion regions 16.

The metal layer 26 may be deposited using a deposition processincluding, for example, chemical vapor deposition, physical vapordeposition, atomic layer deposition, electrodeposition and electrolessdeposition.

The metal layer 26 includes any silicide metal that tends to agglomerateduring subsequent thermal cycles. Illustrative examples of such metalsinclude: Ni, Pd, Pt, and W. In a highly preferred embodiment of thepresent invention, the metal layer 26 is comprised of Ni. When Ni isemployed, it also highly preferred that F ions be implanted in theSi-containing substrate 12.

The metal layer 26 has a sufficient thickness that will allow forstabilized metal silicide contacts to be subsequently formed. Typically,the metal layer 26 has a thickness from about 2 to about 30 nm, with athickness from about 5 to about 15 nm being more typical.

FIG. 3 also shows the presence of an optional cap 28 that is formed atopthe metal layer 26. When present, the optional cap 28 is composed of adiffusion barrier material such as, for example, TiN, Ti, W and WN. Theoptional cap 28 is formed by a conventional deposition process,including, for example, sputtering, evaporation, chemical vapordeposition, chemical solution deposition and the like.

If used, the optional cap 28 has a thickness after deposition that istypically from about S to about 40 nm, with a thickness from about 5 toabout 20 nm being more typical.

The structure shown in FIG. 3 is then subjected to a silicide annealingprocess in which a stabilized metal silicide contact is formed atop atleast the source/drain diffusion regions 16. Note if the gate electrodematerial 22 is SiGe or polysilicon that does not include a hardmask, ametal silicide contact can be formed atop the gate electrode material 22as well.

The annealing process employed in the present invention includes atleast a first anneal and removal of optional cap 28 and any unreactedmetal. An optional second anneal, which follows the removal step, may berequired in some instances if the first anneal does not completely forma phase of the metal silicide having its lowest resistance.

The first anneal is typically performed at lower temperatures than theoptional second annealing step. Typically, the first annealing step isperformed at a temperature from about 200° C. to about 700° C. using acontinuous heating regime or various ramp and soak heating cycles. Morepreferably, the first annealing step is performed at a temperature fromabout 250° C. to about 550° C. Typical annealing times for the firstanneal are from about 1 to about 120 seconds. Longer anneal times, ashigh as about 1 hour, are also contemplated herein. The first annealingstep may form the lowest resistance phase of the metal silicide contactor it can form a metal rich silicide.

When needed, the second annealing step is performed at a temperaturefrom about 250° C. to about 900° C. using a continuous heating regime orvarious ramp and soak heating cycles. More preferably, the secondannealing step is performed at a temperature from about 350° C. to about750° C. Typical annealing times for the second anneal are from about 1to about 120 seconds. Longer anneal times, as high as 2 hours, are alsocontemplated herein. The second anneal typically converts the highresistance metal silicide or metal rich silicide phase into a metalsilicide contact 32 of lower resistance. See FIG. 4.

The silicide anneals are carried out in a gas atmosphere, e.g., He, Ar,N₂ or forming gas. The silicide annealing steps may use differentatmospheres or the annealing steps may be carried out in the sameatmosphere. For example, He may be used in both annealing steps, or Hecan be used in the first annealing step and a forming gas may be used inthe second annealing step.

The selective etching step includes any conventional etching processthat can selectively remove non-reacted metal. Note that this etch alsoremoves the optional cap 28. Examples include wet etching using asulfuric acid/hydrogen peroxide solution. See FIG. 4. After performingthe above steps, further CMOS processing steps for forming an interleveldielectric containing conductively filled contact openings, which are incontact with the metal silicide contact 32 of the present invention, canbe performed.

It is emphasized that the presence of the ions in the Si-containingsubstrate 12 substantially prevents agglomeration of the metal silicideduring subsequent thermal processing. The presence of the ions blocksmetal diffusion into the Si-containing substrate thereby effectivelyincreasing the temperature at which agglomeration of the metal silicidemay occur.

The following example illustrates the method of the present inventionand shows that by performing the inventive processing steps a stabilizedmetal silicide film can be formed that exhibits substantially little orno agglomeration during subsequent high temperature thermal processing.

EXAMPLE

In this example, F⁺ implants were performed on chips and onsilicon-on-insulator (SOI) pieces before Ni (9 nm)/TiN deposition ateither 2 keV or 5 keV. With these energies, most F+ implanted remains inthe part of the Si that will be consumed to form the NiSi. At each ofthe energies, doses of 0.3, 1 and 3E15 per cm² were selected. For one ofthe energy conditions, an extra activation anneal (35° C./0 s to 1000°C., no hold) was performed to evaluate the effect of implantation of theF+ with other species (before activation anneal) or just before Nideposition. The sheet resistance values of SOI samples after deposition,formation anneal, selective etch and anneals at 500° C. for 30 min and600° C. for 30 min are shown in FIGS. 5A-5B. In FIG. 5A, results aregiven for 5 keV F+ implants for which there was no extra activationanneal. In FIG. 5B, results are given when the activation anneal isperformed before metal deposition. These results show that for a 600° C.anneal of 30 min:

-   -   a. The prior art NiSi film (labeled as PA) fully agglomerates        (Rs>1E6 Ohms/sq.)    -   b. A dose of 3E14 without activation anneal (labeled as Curve A        in FIG. 5A) is not sufficient to take full advantage and keep        the lowest sheet resistance    -   c. The activation anneal is not suitable (Rs>1E6) for doses of        3E14 and 1E15 (labeled as Curves A and B in FIG. 5B). This        anneal was not detrimental in the case of the highest F+dose        (labeled as Curve C in FIG. 5B). The anneal drives the F away        from the interface of interest but can still work if the dose is        high enough. Implantation of F+ is more efficient just before        metal deposition.    -   d. All samples that receive a dose of 3E15 maintained the low Rs        of NiSi films (labeled as Curve C in FIGS. 5A and 5B).    -   e. Samples that receive a dose of 1E15 and No activation anneal        also maintained low Rs (labeled as Curve B in FIG. 5A).

For one sample (3E15/2 keV not shown), the Rs was elevated after theselective etch. When the dose of F+ in the top Si layer was too large,the formation of NiSi was delayed significantly as the Rs is closer tothat of metal rich phases.

Therefore doses ranging from 1 to 3E15 at energies ranging from 2 to 5keV were most efficient at reducing agglomeration at 600° C. The delayedformation of NiSi at the higher dose and at the lower energy suggestthat too high a dose may lead to other problems even if they resolve theagglomeration issue.

Stabilization of NiSi with F+implants was also shown in narrowdimensions. The agglomeration of NiSi occurs primarily on narrow singlecrystal areas of chips. In FIGS. 6A-6D, the region of a test structurecontaining poly-Si and Si(100) areas are shown using back scattered SEMafter anneals at 500° C. for 30 minutes (after NiSi formation, 20 nmthick).

The light lines correspond to NiSi on poly-Si while the darker regionsbordering the lines are single crystal Si(100) areas. For the POR sample(prior art; no implants) shown in FIG. 6A, the NiSi on Si(100) areas isclearly agglomerated. Note that for the much narrower areas of NiSi onpoly-Si, the NiSi retains its morphological properties. As the F+dose(at 5 keV) is increased from 3E14 (FIG. 6B) to 5E15 (FIG. 6C), the NiSion Si(100) is much more uniform, i.e., the agglomeration issignificantly retarded. At the highest dose 3E15, 5 keV, the NiSiremains uniform. See FIG. 6D.

While the present invention has been particularly shown and describedwith respect to preferred embodiments thereof, it will be understood bythose skilled in the art that the foregoing and other changes in formsand details may be made without departing from the scope and spirit ofthe present invention. It is therefore intended that the presentinvention not be limited to the exact forms and details described andillustrated, but fall within the scope of the appended claims.

1. A method for forming a stabilized NiSi film comprising: implanting Fions into a surface of a Si-containing layer at an implant energy ofabout 2 keV or less; forming a Ni layer atop the surface of theSi-containing layer containing said F ions; and siliciding the Ni layerand the Si-containing layer containing said F ions to form a NiSi film,said NiSi film exhibits little or no agglomeration during subsequentthermal processing.
 2. The method of claim 1 wherein the Si-containinglayer is a Si-containing substrate that comprises at least one gateregion located on a surface of said substrate.
 3. The method of claim 1wherein the F ions are implanted at an energy from about 0.1 to about 5keV using a dose from about 5E13 to about 5E16 atoms/cm².
 4. The methodof claim 1 further comprising annealing the ions prior to said formingthe metal layer, said annealing is performed in an inert gas ambient ata temperature from about 200° C. to about 1200° C.
 5. The method ofclaim 1 further comprising forming a cap atop the metal layer prior tothe siliciding.
 6. The method of claim 1 wherein the silicidingcomprises a first anneal and removal of unreacted metal.
 7. The methodof claim 6 wherein the first anneal is performed at a temperature fromabout 200° C. to about 700° C.
 8. The method of claim 6 wherein theremoval comprises a selective etch process.
 9. The method of claim 6further comprising a second anneal after said removal, said secondanneal is performed at a temperature that is higher than the firstanneal, wherein said higher temperature ranges from about 250° C. toabout 950° C.
 10. The method of claim 6 wherein said implanting F ionsis performed after standard device ion implantation and activationannealing.
 11. A method of forming a stabilized metal silicide filmcomprising: implanting ions into a surface of a Si-containing layerduring implanting source/drain regions, said ions are capable ofattaching to defects within the Si-containing layer and said ions areselected from the group consisting of Si, H, Ct, Br, Pt, Re, Pd, Rh, Wand In; forming a metal layer atop the surface of the Si-containinglayer containing said ions; and siliciding the metal layer and theSi-containing layer containing said ions to form a metal silicide film,said metal silicide film exhibits little or no agglomeration duringsubsequent thermal processing.